Dimension shuffling using matrix processors

ABSTRACT

In one embodiment, a matrix operation may be performed to reorder a plurality of dimensions of an input matrix stored in two-dimensional memory. Data associated with the input matrix may be accessed using one or more strided memory operations, wherein the one or more strided memory operations are configured to access the two-dimensional memory at a plurality of locations that are separated by a particular interval. The data accessed using the one or more strided memory operations may be stored in a result matrix, wherein the data accessed using each strided memory operation is stored in the result matrix in non-transpose form or transpose form.

FIELD OF THE SPECIFICATION

This disclosure relates in general to the field of computer processing, and more particularly, though not exclusively, to performing matrix operations.

BACKGROUND

Matrix operations, such as matrix multiplication and convolutions, can be highly processor-intensive and memory-intensive operations, as they often involve complex operations on large, multi-dimensional matrix operands. Accordingly, the performance of complex matrix operations can be limited by the processing and/or memory latency. As matrix operations are increasingly utilized in a variety of applications and with ever-growing data sets (from graphics and image processing to machine learning and artificial intelligence), the demand for high-performance processing of matrix operations is increasing.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not necessarily drawn to scale, and are used for illustration purposes only. Where a scale is shown, explicitly or implicitly, it provides only one illustrative example. In other embodiments, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 illustrates a schematic diagram for an example computing system according to certain embodiments.

FIGS. 2A-C illustrate block diagrams for an example embodiment of a matrix processing architecture.

FIGS. 3 and 4 illustrate block diagrams for example embodiments of computer processors.

FIGS. 5A-D illustrate examples of matrix dimension shuffling.

FIG. 6 illustrates a flowchart for an example embodiment of matrix dimension shuffling.

EMBODIMENTS OF THE DISCLOSURE

The following disclosure provides many different embodiments, or examples, for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Different embodiments may have different advantages, and no particular advantage is necessarily required of any embodiment.

Matrix processing operations (e.g., linear algebra operations that involve matrix and/or vector operands) have a wide range of applications in computing systems, from graphics processing to machine learning and artificial intelligence, among other examples. For example, complex matrix operations may be used to implement artificial neural networks that provide artificial intelligence and machine learning capabilities, including computer vision, autonomous navigation, speech and audio recognition, and natural language processing, among other examples. These complex matrix operations (e.g., matrix multiplication and convolutions) may be used to implement the fundamental operations of neural networks, such as forward propagation, backward propagation, and weight updates. These matrix operations, however, can be highly processor and memory intensive, as they often involve complex operations on large, multi-dimensional matrix operands. Accordingly, the performance of these matrix operations can be limited by processing and/or memory latency. As matrix operations are increasingly utilized in a variety of applications with ever-growing data sets, such as artificial intelligence and machine learning, the demand for high-performance processing of matrix operations is increasing.

Existing matrix processing approaches suffer from various inefficiencies, particularly when used to implement artificial intelligence and machine learning in artificial neural networks. For example, existing matrix processing approaches are inefficient for certain matrix operations, such as matrix multiplication or convolution operations involving large matrix operands and/or matrix operands with certain dimensions, among other examples. While central processing units (CPUs) could be used to perform matrix operations, many CPU processing architectures are designed for low arithmetic intensity operations (i.e., a low ratio of arithmetic operations relative to memory operations), and thus are not designed for efficient execution of matrix operations. Moreover, many CPU architectures utilize complex local or cache memory management routines, which may increase processing overhead and execution complexity for operations involving large matrix operands. Graphics processing units (GPUs) could also be used to perform matrix operations. GPUs, however, are often designed for high precision computations and may provide a level of precision that is unnecessary for certain matrix operations, thus reducing the volume of matrix operations that can be performed.

Existing matrix processing approaches are also inefficient for matrix dimension shuffling. Matrix dimension shuffling may be used by certain matrix operations (e.g., convolution operations) to reorder the dimensions of a matrix in memory. While matrix dimension shuffling could be performed using CPUs, CPUs are unable to efficiently perform other complex matrix operations (e.g., matrix multiplication and convolutions). Moreover, while complex matrix operations (e.g., matrix multiplication and convolutions) could be performed using GPUs or other matrix-based processing architectures, those architectures are unable to efficiently perform matrix dimension shuffling (and they are also unable to perform complex matrix operations with 100% processing efficiency). Finally, CPUs could be used to perform matrix dimension shuffling while offloading other complex matrix operations to GPUs or other matrix-based processing architectures, but that approach would require additional transmissions of large matrix operands between the CPUs and the GPUs (or other matrix-based processing architectures), resulting in increased overhead and reduced processing efficiency.

The matrix processing functionality described throughout this disclosure can be used to efficiently perform both matrix dimension shuffling operations and other complex matrix operations (e.g., matrix multiplication and convolutions). For example, certain embodiments may utilize a processing architecture that is optimized for matrix operations, which may include memory components designed to store matrix operands, such as two-dimensional (2D) memory components. For example, 2D memory may include memory that is configured to store and retrieve data in two dimensions, such as using rows and columns. In some embodiments, the 2D memory may be used to store matrix operands with two or more dimensions. For example, the 2D memory may be used to store a matrix with two dimensions (e.g., a matrix with dimensions A and B, or A×B), or a matrix with three dimensions (e.g., a matrix with dimensions A, B, and C, or A×B×C). In some embodiments, for example, a three-dimensional (3D) matrix with dimensions A×B×C may be stored in 2D memory with its dimensions arranged as AB×C, AC×B, BA×C, BC×A, or A×BC, and so forth. In some cases, however, a particular matrix operation (e.g., a convolution operation) may need the dimensions of a matrix converted from one arrangement in memory to another arrangement in memory (e.g., converting a matrix stored as AB×C to BA×C). Thus, in some embodiments, a dimension shuffle operation may be used to reorder the dimensions of a matrix in memory.

In some embodiments, dimension shuffling may be implemented using strided memory access. For example, some embodiments may include a convolutional read operation, which may use strided memory access to read data at locations in 2D memory that are separated by a particular interval or stride. Moreover, some embodiments may include multiple variations of the convolutional read operation, which may be used to store data obtained using strided memory access in different forms. For example, in some embodiments, dimension shuffling may be implemented using non-transpose convolutional reads and transpose convolutional reads. A non-transpose convolutional read, for example, may store data obtained using strided memory access in a result matrix in non-transpose form. A transpose convolutional read, for example, may store data obtained using strided memory access in a result matrix in transpose form. In this manner, any dimension shuffle operation may be performed using one or more non-transpose and/or transpose convolutional reads.

The matrix processing functionality described throughout this disclosure provides numerous technical advantages, including alleviating the inefficiencies of existing approaches and enabling matrix operations (e.g., dimension shuffle operations and other complex matrix operations) to be executed efficiently. For example, any dimension shuffle operation may be performed to reorder the dimensions of a matrix from one format to another using a minimum number of conversions. These advantages result in reduced processing time for matrix operations, which improves performance for applications that involve complex matrix operations, such as artificial intelligence and machine learning functionality implemented using artificial neural networks (e.g., convolutional neural networks, multilayer perceptrons (MLPs), restricted Boltzmann machines (RBM), and deep belief networks (DBN), among other examples).

Example embodiments that may be used to implement the matrix processing functionality of this disclosure will now be described with more particular reference to the attached FIGURES.

FIG. 1 illustrates a schematic diagram for an example computing system 100 according to certain embodiments.

In some embodiments, the matrix processing functionality described throughout this disclosure may be implemented in system 100. Matrix processing functionality may be used in system 100 for a wide range of applications and/or use cases involving matrix operations, from graphics processing to machine learning and artificial intelligence, among other examples. For example, in some embodiments, matrix processing functionality may be used to implement artificial intelligence and machine learning in artificial neural networks. Moreover, matrix processing functionality may be implemented by any component of system 100. For example, in the illustrated embodiment, system 100 includes edge devices 110, cloud services 120, matrix processing nodes 130, and network 150. Matrix processing nodes 130 may include any component or device with matrix processing functionality, including any component of system 100. For example, matrix processing nodes 130 may include cloud services 120 and/or servers implemented with matrix processing functionality (e.g., application servers in a datacenter), edge devices 110 implemented with matrix processing functionality (e.g., end-user devices 112, Internet-of-Things devices 114, gateways 116), and so forth. These various components of system 100 are discussed further below.

Edge devices 110 may include any equipment and/or devices deployed or connected near the “edge” of a communication system 100. Edge devices 110 may communicate with each other and/or with other remote networks and services (e.g., cloud services 120) through one or more networks and/or communication protocols, such as network 150. In some embodiments, certain edge devices 110 may include the matrix processing functionality described throughout this disclosure, and thus may be used as matrix processing nodes 130. In the illustrated embodiment, edge devices 110 include end-user devices 112 (e.g., desktops, laptops, mobile devices), Internet-of-Things (IoT) devices 114, and gateways and/or routers 116, among other examples.

End-user devices 112 may include any device that enables or facilitates user interaction with computing system 100, including, for example, desktop computers, laptops, tablets, mobile phones and other mobile devices, and wearable devices (e.g., smart watches, smart glasses, headsets), among other examples.

IoT devices 114 may include any device capable of communicating and/or participating in an Internet-of-Things (IoT) system or network. IoT systems may refer to new or improved ad-hoc systems and networks composed of multiple different devices (e.g., IoT devices 114) interoperating and synergizing for a particular application or use case. Such ad-hoc systems are emerging as more and more products and equipment evolve to become “smart,” meaning they are controlled or monitored by computer processors and are capable of communicating with other devices. For example, an IoT device 114 may include a computer processor and/or communication interface to allow interoperation with other components of system 100, such as with cloud services 120 and/or other edge devices 110. IoT devices 114 may be “greenfield” devices that are developed with IoT capabilities from the ground-up, or “brownfield” devices that are created by integrating IoT capabilities into existing legacy devices that were initially developed without IoT capabilities. For example, in some cases, IoT devices 114 may be built from sensors and communication modules integrated in or attached to “things,” such as equipment, toys, tools, vehicles, living things (e.g., plants, animals, humans), and so forth. Alternatively, or additionally, certain IoT devices 114 may rely on intermediary components, such as edge gateways or routers 116, to communicate with the various components of system 100.

IoT devices 114 may include various types of sensors for monitoring, detecting, measuring, and generating sensor data and signals associated with characteristics of their environment. For instance, a given sensor may be configured to detect one or more respective characteristics, such as movement, weight, physical contact, temperature, wind, noise, light, position, humidity, radiation, liquid, specific chemical compounds, battery life, wireless signals, computer communications, and bandwidth, among other examples. Sensors can include physical sensors (e.g., physical monitoring components) and virtual sensors (e.g., software-based monitoring components). IoT devices 114 may also include actuators to perform various actions in their respective environments. For example, an actuator may be used to selectively activate certain functionality, such as toggling the power or operation of a security system (e.g., alarm, camera, locks) or household appliance (e.g., audio system, lighting, HVAC appliances, garage doors), among other examples.

Indeed, this disclosure contemplates use of a potentially limitless universe of IoT devices 114 and associated sensors/actuators. IoT devices 114 may include, for example, any type of equipment and/or devices associated with any type of system 100 and/or industry, including transportation (e.g., automobile, airlines), industrial manufacturing, energy (e.g., power plants), telecommunications (e.g., Internet, cellular, and television service providers), medical (e.g., healthcare, pharmaceutical), food processing, and/or retail industries, among others. In the transportation industry, for example, IoT devices 114 may include equipment and devices associated with aircrafts, automobiles, or vessels, such as navigation systems, autonomous flight or driving systems, traffic sensors and controllers, and/or any internal mechanical or electrical components that are monitored by sensors (e.g., engines). IoT devices 114 may also include equipment, devices, and/or infrastructure associated with industrial manufacturing and production, shipping (e.g., cargo tracking), communications networks (e.g., gateways, routers, servers, cellular towers), server farms, electrical power plants, wind farms, oil and gas pipelines, water treatment and distribution, wastewater collection and treatment, and weather monitoring (e.g., temperature, wind, and humidity sensors), among other examples. IoT devices 114 may also include, for example, any type of “smart” device or system, such as smart entertainment systems (e.g., televisions, audio systems, videogame systems), smart household or office appliances (e.g., heat-ventilation-air-conditioning (HVAC) appliances, refrigerators, washers and dryers, coffee brewers), power control systems (e.g., automatic electricity, light, and HVAC controls), security systems (e.g., alarms, locks, cameras, motion detectors, fingerprint scanners, facial recognition systems), and other home automation systems, among other examples. IoT devices 114 can be statically located, such as mounted on a building, wall, floor, ground, lamppost, sign, water tower, or any other fixed or static structure. IoT devices 114 can also be mobile, such as devices in vehicles or aircrafts, drones, packages (e.g., for tracking cargo), mobile devices, and wearable devices, among other examples. Moreover, an IoT device 114 can also be any type of edge device 110, including end-user devices 112 and edge gateways and routers 116.

Edge gateways and/or routers 116 may be used to facilitate communication to and from edge devices 110. For example, gateways 116 may provide communication capabilities to existing legacy devices that were initially developed without any such capabilities (e.g., “brownfield” IoT devices). Gateways 116 can also be utilized to extend the geographical reach of edge devices 110 with short-range, proprietary, or otherwise limited communication capabilities, such as IoT devices 114 with Bluetooth or ZigBee communication capabilities. For example, gateways 116 can serve as intermediaries between IoT devices 114 and remote networks or services, by providing a front-haul to the IoT devices 114 using their native communication capabilities (e.g., Bluetooth, ZigBee), and providing a back-haul to other networks 150 and/or cloud services 120 using another wired or wireless communication medium (e.g., Ethernet, Wi-Fi, cellular). In some embodiments, a gateway 116 may be implemented by a dedicated gateway device, or by a general purpose device, such as another IoT device 114, end-user device 112, or other type of edge device 110.

In some instances, gateways 116 may also implement certain network management and/or application functionality (e.g., IoT management and/or IoT application functionality for IoT devices 114), either separately or in conjunction with other components, such as cloud services 120 and/or other edge devices 110. For example, in some embodiments, configuration parameters and/or application logic may be pushed or pulled to or from a gateway device 116, allowing IoT devices 114 (or other edge devices 110) within range or proximity of the gateway 116 to be configured for a particular IoT application or use case.

Cloud services 120 may include services that are hosted remotely over a network 150, or in the “cloud.” In some embodiments, for example, cloud services 120 may be remotely hosted on servers in datacenter (e.g., application servers or database servers). Cloud services 120 may include any services that can be utilized by or for edge devices 110, including but not limited to, data storage, computational services (e.g., data analytics, searching, diagnostics and fault management), security services (e.g., surveillance, alarms, user authentication), mapping and navigation, geolocation services, network or infrastructure management, IoT application and management services, payment processing, audio and video streaming, messaging, social networking, news, and weather, among other examples. In some embodiments, certain cloud services 120 may include the matrix processing functionality described throughout this disclosure, and thus may be used as matrix processing nodes 130.

In general, edge devices 110 (and in particular IoT devices 114) may generate an extremely large volume and variety of data. IoT edge devices 114 typically offload this data to the cloud for processing and/or storage (e.g., by cloud services 120). Cloud services 120, however, may not necessarily be suited to handle the rapidly growing volume, variety, and velocity of data generated by IoT devices 114 and other edge devices 110. For example, cloud-based processing may not be ideal in certain circumstances, such as processing time-sensitive or highly confidential data, or when faced with network bandwidth constraints, among other examples. In some embodiments, cloud services 120 may leverage “edge” based processing using edge devices 110 to improve the performance of cloud services. Edge processing is an approach that involves processing certain data at the network edge (e.g., using edge devices 110), near where the data is generated, rather than simply funneling large volumes of data to the cloud for processing and storage. Certain data may still be sent to the cloud, as appropriate, such as for deeper analysis and/or long-term storage. Edge processing may be used to complement the shortcomings of cloud-based processing (e.g., when cloud-based processing is inefficient, ineffective, and/or unsecure), and thus improve the handling of the growing volume, variety, and velocity of data generated by IoT devices 114 and/or other edge devices 110. For example, in some cases, processing data near its source (e.g., in the network edge) rather than in the cloud may improve performance and/or avoid system failures or disasters. Edge processing may also conserve network bandwidth, which may be particularly beneficial when facing bandwidth constraints and/or limited network connectivity.

In some embodiments, edge devices 110 that provide edge-based processing for cloud services 120 may be collectively referred to as the “fog,” as they serve to extend the “cloud” to the edge of the network, thus creating a “fog” over the network edge. In some embodiments, devices 110 in the “fog” may connect and/or communicate with each other, for example, using an interconnection standard or protocol. For example, in some embodiments, device interconnection may be implemented using the open interconnect consortium (OIC) standard specification 1.0, released by the Open Connectivity Foundation™ (OCF) on Dec. 23, 2015, which enables devices to discover and connect with each other. Another interconnection protocol that may be used is Thread, a networking protocol for Internet-of-Things (IoT) devices used in “smart” home automation and similar deployments, which has been developed by an alliance of organizations named the “Thread Group.” Other interconnection protocols may also be used, including, for example, the optimized link state routing (OLSR) protocol, or the better approach to mobile ad-hoc networking (B.A.T.M.A.N.), among others.

Network 150 may be used to facilitate communication between the components of computing system 100. For example, edge devices 110, such as end-user devices 112 and IoT devices 114, may use network 150 to communicate with each other and/or access one or more remote cloud services 120. Network 150 may include any number or type of communication networks, including, for example, local area networks, wide area networks, public networks, the Internet, cellular networks, Wi-Fi networks, short-range networks (e.g., Bluetooth or ZigBee), and/or any other wired or wireless networks or communication mediums.

Any, all, or some of the computing devices of system 100 may be adapted to execute any operating system, including Linux or other UNIX-based operating systems, Microsoft Windows, Windows Server, MacOS, Apple iOS, Google Android, or any customized and/or proprietary operating system, along with virtual machines adapted to virtualize execution of a particular operating system.

While FIG. 1 is described as containing or being associated with a plurality of elements, not all elements illustrated within system 100 of FIG. 1 may be utilized in each alternative implementation of the present disclosure. Additionally, one or more of the elements described in connection with the examples of FIG. 1 may be located external to system 100, while in other instances, certain elements may be included within or as a portion of one or more of the other described elements, as well as other elements not described in the illustrated implementation. Further, certain elements illustrated in FIG. 1 may be combined with other components, as well as used for alternative or additional purposes in addition to those purposes described herein.

Example Matrix Processing Architecture

FIGS. 2A-C illustrate block diagrams for an example embodiment of a matrix processing architecture.

In some embodiments, the matrix processing functionality described throughout this disclosure may be implemented using a matrix processing architecture, such as the matrix processing architecture of FIGS. 2A-2C. Matrix processing architectures, such as the matrix processing architecture of FIGS. 2A-2C, may be implemented or used in a variety of systems, devices, and/or components, such as those described throughout this disclosure, including system 100 of FIG. 1 and/or any of its associated components (e.g., cloud services 120/datacenter servers, edge devices 110, matrix processing nodes 130). In some embodiments, the matrix processing architecture of FIGS. 2A-2C may be used to implement artificial intelligence and machine learning in neural networks. The matrix processing architecture illustrated in FIGS. 2A-2C is merely one example embodiment for performing the matrix processing functionality described throughout this disclosure. Other embodiments may use different types, arrangements, and/or numbers of components. For example, other embodiments may include any number of matrix processing chips 220, matrix processing clusters 230, matrix processing units (MPUs) 234, high bandwidth memory (HBM) modules 240, and/or memory resource blocks (MRBs) 238. Moreover, all or part of any component of the matrix processing architecture of FIGS. 2A-2C (e.g., any component of matrix processing system 200, matrix processing chips 220, and/or matrix processing clusters 230) may be implemented as a separate or stand-alone component or chip, or may be integrated with other components or chips, such as a system-on-a-chip (SoC) that integrates various computer components into a single chip.

FIG. 2A illustrates a block diagram for an example embodiment of a matrix processing system 200. In the illustrated embodiment, matrix processing system 200 includes host processor 260, host memory 270, matrix processing resources 210, and interconnect bus 280.

Host processor 260 may be configured to control and/or manage matrix processing system 200. For example, in some embodiments, host processor 260 may use matrix processing resources 210 to perform complex matrix operations. Host processor 260 may be any processing resource capable of controlling and/or managing matrix processing functionality of matrix processing system 200. For example, in some embodiments, host processor 260 may be implemented using computer processors 300 or 400 of FIGS. 3 and 4, respectively. In some embodiments, host processor 260 may be a separate or stand-alone component that is communicatively coupled to matrix processing resources 210. Alternatively, in other embodiments, host processor 260 and matrix processing resources 210 may be integrated into the same component or chip. For example, in some embodiments, the components of matrix processing system 200, including host processor 260 and matrix processing resources 210, may be implemented as a system-on-a-chip (SoC).

Host memory 270 may include any type or combination of volatile and/or non-volatile memory. Examples of volatile memory include various types of random access memory (RAM), such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and static random access memory (SRAM), among other examples. Examples of non-volatile memory include disk-based storage mediums (e.g., magnetic and/or optical storage mediums), solid-state storage (e.g., any form of persistent flash memory, including planar or three dimensional (3D) NAND flash memory or NOR flash memory), 3D crosspoint memory, electrically erasable programmable read-only memory (EEPROM), and/or other types of non-volatile random access memories (RAM), among other examples. Host memory 270 may be used, for example, to store information for host processor 260 during execution, such as code and/or data.

Interconnect bus 280 may be used, in some embodiments, to communicatively couple host processor 260 and host memory 270 to matrix processing resources 210. Interconnect bus 280 may use any interconnection protocol, such as Peripheral Component Interconnect express (PCIe), Universal Serial Bus (USB), or Small Computer Systems Interface (SCSI), among other examples.

Matrix processing resources 210 may include any processing resources configured to perform matrix operations. For example, matrix processing resources 210 may be configured to perform matrix multiplication operations, convolution operations, element-wise matrix operations (e.g., +, *, / <, >, ==), dimension shuffle operations, and/or any combination thereof. In some embodiments, matrix processing resources 210 may include processing resources that are designed and optimized for performing matrix operations. In some embodiments, matrix processing resources 210 may also be arranged hierarchically with multiple levels of processing resources. For example, in the illustrated embodiment, matrix processing resources 210 include a plurality of matrix processing chips 220, and may also include any processing resources within each matrix processing chip 220. For example, as discussed below in connection with FIGS. 2B and 2C, each matrix processing chip 220 may include a plurality of high bandwidth memory (HBM) modules and a plurality of matrix processing clusters 230, and each matrix processing cluster 230 may include multiple matrix processing units 234. Thus, in some embodiments, matrix processing resources 210 may include multiple matrix processing chips 220, multiple high bandwidth memory (HBM) modules and multiple matrix processing clusters 230 on each matrix processing chip 220, and/or multiple matrix processing units 234 on each matrix processing cluster 230.

Matrix processing chips 220 may be, for example, any chips or other components configured to perform matrix operations. For example, in some embodiments, a matrix processing chip 220 may be a peripheral card or chip connected to host processor 260 using any type of interconnect interface, such as a PCIe interface. In some embodiments, a matrix processing chip 220 may be implemented using an integrated circuit, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), and/or any other type of circuitry. In the illustrated embodiment, matrix processing chips 220 are configured in a cyclical arrangement, with communication channels 215 between neighboring matrix processing chips 220. In some embodiments, communication channels 215 may provide one-way communication between neighboring matrix processing chips 220. In other embodiments, however, communication channels 215 may provide bi-directional communication between neighboring matrix processing chips 220. A cyclical arrangement with one-way communication between neighboring processing resources may be referred to as a “single-cyclical” configuration, while a cyclical arrangement with bi-directional communication between neighboring processing resources may be referred to as a “dual-cyclical” configuration.

FIG. 2B illustrates a block diagram for an example embodiment of a matrix processing chip 220. In the illustrated embodiment, matrix processing chip 220 includes controller 222, host interface 224, inter-chip links 225, high bandwidth memory (HBM) modules 240, and matrix processing clusters 230.

Controller 222 may be configured to control and/or manage matrix operations performed by matrix processing chip 220. In some embodiments, controller 222 may control and/or manage matrix operations in conjunction with host processor 260 of FIG. 2A and/or master control CPUs (MCCs) 232 of matrix processing clusters 230 of FIG. 2C. For example, in some embodiments, host processor 260, controller 222, and/or master control CPUs (MCCs) 232 may be configured to receive a matrix operation or command, and distribute the matrix operation and matrix operands across matrix processing clusters 230 and high bandwidth memory (HBM) modules 240. In some embodiments, controller 222 may be a microprocessor, an integrated circuit, and/or any other type of circuitry and/or processing logic.

Host interface 224 may be a communication interface that enables a matrix processing chip 220 to communicate with host processor 260 of FIG. 2A. In some embodiments, for example, controller 222 may use host interface 224 to communicate with host processor 260 of FIG. 2A. Host interface 224 may use any type of interconnect protocol or interface, including Peripheral Component Interconnect express (PCIe), Universal Serial Bus (USB), or Small Computer Systems Interface (SCSI), among other examples.

Inter-chip links (ICLs) 225 may enable a matrix processing chip 220 to communicate with other matrix processing chips. For example, inter-chip links 225 may be used to implement the communication channels 215 between matrix processing chips 220 in FIG. 2A. An inter-chip link 225 may be, for example, any communication interface that enables a matrix processing chip 220 to communicate with another matrix processing chip. In some embodiments, a matrix processing chip 220 may include multiple inter-chip links 225 (e.g., twelve inter-chip links). In some embodiments, an inter-chip link 225 may be implemented using one or more serializer/de-serializer (SerDes) interfaces. A SerDes interface may be a communication interface that converts data from serial to parallel, and vice-versa. For example, the transmitter of a SerDes interface may include a serial-to-parallel converter, and the receiver of a SerDes interface may include a parallel-to-serial converter. In some embodiments, a matrix processing chip 220 may use multiple SerDes interfaces for each connection to another matrix processing chip (e.g., four SerDes interfaces between each pair of connected matrix processing chips).

High bandwidth memory (HBM) modules 240 may be memory components associated with matrix processing chip 220 that are used to store matrix operands and other matrix data. In some embodiments, high bandwidth memory (HBM) modules 240 may be designed to efficiently store and retrieve matrix data. In some embodiments, high bandwidth memory (HBM) modules 240 may be multi-dimensional memory components configured to store and retrieve data in multiple dimensions. For example, in some embodiments, high bandwidth memory (HBM) modules 240 may be memory components configured to store and retrieve data in two dimensions, such as rows and columns. Other embodiments, however, may use memory components configured to store and retrieve data using any other number of dimensions (e.g., one dimension, three dimensions, four dimensions, and so forth). In the illustrated embodiment, matrix processing chip 220 includes four high bandwidth memory (HBM) modules 240 a-d. In some embodiments, high bandwidth memory (HBM) modules 240 may be shared by the matrix processing clusters 230 of a matrix processing chip 220.

Matrix processing clusters 230 may include processing resources configured to perform matrix operations, such as matrix multiplication, convolutions, and/or dimension shuffling, among other examples. In some embodiments, matrix processing clusters 230 may be collectively used to execute a particular matrix operation by performing matrix processing in parallel. In the illustrated embodiment, matrix processing chip 220 includes twelve matrix processing clusters 230 a-l. Moreover, in the illustrated embodiment, matrix processing clusters 230 are configured or arranged using a two-dimensional mesh interconnection topology. The interconnection topology of matrix processing clusters 230 may facilitate cyclical communication among the matrix processing clusters 230. Moreover, other embodiments may include any number and/or arrangement of matrix processing clusters 230.

FIG. 2C illustrates a block diagram for an example embodiment of a matrix processing cluster 230. In the illustrated embodiment, matrix processing cluster 230 includes master control CPU (MCC) 232, matrix processing units (MPUs) 234, slicing engine 236, and memory resource blocks (MRBs) 238.

Master control CPU (MCC) 232 may be configured to control and/or manage matrix operations performed by a matrix processing cluster 230. In some embodiments, master control CPU 232 may be a microprocessor, an integrated circuit, and/or any other type of circuitry and/or processing logic. In some embodiments, master control CPU 232 may receive instructions from another component, such as host processor 260 of FIG. 2A and/or controller 222 of FIG. 2B. Based on the instructions, master control CPU 232 may then use matrix processing units 234 to perform matrix operations, such as matrix multiplication, convolutions, and/or dimension shuffling, among other examples. For example, master control CPU 232 may receive an instruction to perform a matrix multiplication operation, such as C=A*B. The instruction may include the handles or identifiers for each matrix, and may also indicate how the matrices should be stored in memory resource blocks (MRBs) 238. Matrices A and B may then be broken down into a series of smaller matrices (e.g., 32×32 matrices). Matrix operations may then be performed on the smaller matrices, and the partial results may be stored in memory resource blocks (MRBs) 238, until the output matrix C has been fully computed.

Matrix processing units (MPUs) 234 may be configured to perform matrix operations, such as matrix multiplication, convolutions, and/or dimension shuffling. In some embodiments, matrix processing units (MPUs) 234 perform matrix operations based on commands received from master control CPU (MCC) 232. Moreover, in some embodiments, each matrix processing cluster 230 may include multiple matrix processing units (MPUs) 234. For example, in the illustrated embodiment, matrix processing cluster 230 includes two matrix processing units (MPUs) 234. A matrix processing unit (MPU) 234 may be capable of performing matrix operations, such as matrix multiplication, on small matrices (e.g., 32×32 matrices). In some cases, a matrix processing unit (MPU) 234 may be designed and/or optimized to perform matrix multiplication operations. A matrix processing unit (MPU) 234 may load matrix operands from memory resource blocks (MRBs) 238. In some embodiments, a matrix processing unit (MPU) 234 may support the following arithmetic operations: matrix multiplication; unary matrix operations; binary matrix operations, such as addition (+), subtraction (−), multiplication (*), division (/), bitwise XOR, AND, OR, logical and arithmetic left and right shift, comparison (>, <, >=, <=, ==, !=); and column-wise, row-wise, and matrix-wide operations, such as sum, max value, and min value.

Slicing engine 236 may be configured to slice the matrix operands of a particular matrix operation into smaller partial matrices. For example, in some embodiments, master control CPU (MCC) 232 may use slicing engine 236 to break up matrix operands into smaller partial matrices for matrix processing units (MPUs) 234. In some embodiments, slicing engine 236 may include a convolution slicing engine (CSE) to perform matrix slicing for convolution operations. For example, in some embodiments, a convolution slicing engine (CSE) may slice matrix operands in a manner that enables a convolution operation to be cast as a matrix multiplication operation, thus enabling the same processing logic to perform both matrix multiplication and convolution operations. Moreover, in some embodiments, slicing engine 236 and/or the associated convolution slicing engine (CSE) may be used to perform the dimension shuffle operations described throughout this disclosure.

Memory resource blocks (MRBs) 238 may be memory components on matrix processing cluster 230 used to store matrix operands and other matrix data. In some embodiments, memory resource blocks (MRBs) 238 may be designed to store and retrieve matrix data efficiently. In some embodiments, memory resource blocks (MRBs) 238 may be multi-dimensional memory components configured to store and retrieve data in multiple dimensions. For example, in some embodiments, memory resource blocks (MRBs) 238 may be memory components configured to store and retrieve data in two dimensions, such as rows and columns. In the illustrated embodiment, matrix processing cluster 230 includes ten memory resource blocks (MRBs) 238. Other embodiments, however, may include a different number of memory resource blocks (MRBs) 238 on a matrix processing cluster 230. In some embodiments, each memory resource block (MRB) 238 may be capable of storing a matrix of a certain size (e.g., a 256×512 matrix). In some embodiments, memory resource blocks (MRBs) 238 may be shared by the matrix processing units (MPUs) 234 of a particular matrix processing cluster 230.

In some embodiments, the matrix processing architecture of FIGS. 2A-2C may be used to implement the matrix processing functionality described throughout this disclosure. For example, matrix processing system 200 may be used to perform matrix operations using a distributed approach that achieves 100% processing efficiency using the available processing resources. For example, in some embodiments, a matrix operation may be distributed across multiple processing resources 210 that are optimized for matrix processing, thus enabling full utilization of the processing resources 210 throughout the duration of the matrix operation. For example, matrix processing system 200 may include multiple processing resources 210 that are designed and optimized for performing matrix operations. In some embodiments, these processing resources 210 may be configured in a single-cyclical or dual-cyclical arrangement. In addition, the processing resources 210 may be arranged hierarchically with multiple levels of processing resources. For example, in some embodiments, the processing resources 210 may include multiple matrix processing chips 220, multiple high bandwidth memory (HBM) modules 240 and multiple matrix processing clusters 230 on each matrix processing chip 220, and/or multiple matrix processing units (MPUs) 234 on each matrix processing cluster 230. This processing architecture enables matrix operations to be distributed across multiple processing resources 210 and/or processing hierarchies with 100% processing efficiency. In addition, this processing architecture enables matrix operations to be efficiently scaled across a variable number of processing resources 210 operating in parallel, while still achieving 100% processing efficiency. For example, scaling may be achieved by adjusting the number of processing resources 210 used to perform a particular matrix operation, such as the number of matrix processing systems 200 or servers, the number of matrix processing chips 220 in each matrix processing system 200 or server, and so forth.

As an example, the matrix processing architecture of FIGS. 2A-2C may be used to implement matrix multiplication and/or convolution operations. For example, in some embodiments, a matrix multiplication operation may be distributed across multiple processing resources 210 in a manner that results in the latency for communicating matrix operands being less than the matrix processing time, which allows the communication of matrix operands to be completed while the matrix processing is being performed. For example, for certain matrix operations involving matrix operands with certain dimensions (e.g., matrix multiplication with a “thin” matrix operand), the time required to access and communicate matrix operands may exceed the time required to perform the actual matrix computations, resulting in idle processing time while the matrix operands are being obtained from memory and/or communicated to processing resources 210. For example, a single-cyclical configuration (e.g., where each processing resource 210 only obtains matrix operands and data from one neighboring processing resource 210 at any given time) may be unable to achieve 100% processing efficiency for these particular types of matrix operations and matrix operands. However, a dual-cyclical configuration of processing resources 210 enables each processing resource to perform matrix computations while simultaneously obtaining matrix operands and data from both of its neighboring processing resources 210, which significantly reduces the latency for communicating matrix operands, and thus avoids any idle processing time. For example, the communication latency for certain operations may be reduced by half when using a dual-cyclical approach as opposed to a single-cyclical approach. In this manner, the latency for communicating matrix operands and matrix data can be fully masked by the matrix processing time, thus avoiding any wasted or idle processing time and achieving 100% processing efficiency. Accordingly, matrix operations (e.g., matrix multiplication or GEMM) can be performed efficiently even for large matrix operands and/or matrix operands with certain dimensions, such as a large matrix operand that is neither square nor a single vector (e.g., a “thin” matrix with a much larger height than width). For example, matrix multiplication can be performed efficiently even when multiplying two thin matrices, a thin matrix and a square matrix, and so forth. Similarly, convolution operations may be distributed across multiple processing resources 210 in a manner that results in 100% processing efficiency using the available processing resources.

As an example, when a matrix operation or command is received, the matrix operation may be distributed across the processing resources 210 of matrix processing system 200. For example, the matrix operands (or input matrices) may be partitioned based on the number of available processing resources 210. Moreover, in some embodiments, the partitions may be across the rows of the matrix operands, and/or across any other dimension of the matrix operands. Each partition may then be distributed to a particular processing resource 210. Each processing resource 210 may then perform a plurality of partial matrix operations. In some embodiments, the plurality of partial matrix operations is performed in a plurality of stages. For example, each processing resource 210 may perform a particular stage of partial matrix operations while simultaneously sending and receiving partial matrix data to and from its neighboring processing resources 210. For example, in a single-cyclical configuration of processing resources 210, each processing resource 210 may send or receive partial matrix data to or from each neighboring processing resource 210. Similarly, in a dual-cyclical configuration of processing resources 210, each processing resource 210 may send and receive partial matrix data to and from each neighboring processing resource 210. Each processing resource 210 may then use the partial matrix data for subsequent partial matrix operations. The result of the matrix operation may then be determined based on the partial matrix operations collectively performed by the processing resources 210.

Moreover, if the processing resources 210 are arranged hierarchically, the matrix operation may be distributed in a hierarchical manner. For example, the matrix operands (or input matrices) may initially be partitioned based on the number of available matrix processing chips 220. Each partition, and the associated partial matrix operations, may then be distributed to a particular matrix processing chip 220. The partition and partial matrix operations distributed to a particular matrix processing chip 220 may then be similarly partitioned and distributed across the matrix processing clusters 230 and/or high bandwidth memory (HBM) modules 240 of the particular matrix processing chip 220. For example, for certain matrix operations, partial matrix operations may be distributed to each matrix processing cluster 230. Alternatively, for certain matrix operations, partial matrix operations may be distributed across various “logical processing nodes” (e.g., groups of matrix processing clusters 230 associated with a high-bandwidth memory (HBM) module 240), and may then be distributed to each matrix processing cluster 230 of a particular logical processing node. In some embodiments, the matrix processing clusters 230 (and/or the logical processing nodes) may be cyclically configured similar to the matrix processing chips 220. The partition and partial matrix operations distributed to a particular matrix processing cluster 230 may then be similarly partitioned and distributed across the matrix processing units (MPUs) 234 of the particular matrix processing cluster 230.

The matrix processing architecture of FIGS. 2A-2C may also be used to implement convolution operations. Convolution operations may be used, for example, for image processing, such as image processing used by an artificial neural network to provide computer vision artificial intelligence and machine learning capabilities. For example, in some embodiments, convolution operations may be used to implement the fundamental operations of an artificial neural network, including forward propagation, backward propagation, and weight updates. A convolution operation used for image processing may involve applying a filter to an image. The filter (which may also be referred to as a “kernel”) may be used to modify the image (e.g., applying visual effects), detect certain features in the image (e.g., facial recognition or identification of other objects), and so forth. In some embodiments, the filter may be smaller than the image, and the convolution operation may be performed by moving the filter throughout the image and applying the filter at each location.

Moreover, in some embodiments, the image and filter of a convolution operation may be represented as matrices. For example, an image may be represented by a matrix whose elements correspond to each pixel of the image. For example, in some embodiments, a black and white image may be represented by a two-dimensional (2D) matrix with dimensions corresponding to the height (H) and width (W) of the image. As another example, a color image may be represented by a three-dimensional (3D) matrix with dimensions corresponding to the height (H), width (W), and channels (C) of the image. The channels of the image, for example, may be used to define the color of each pixel in the image. For example, in some embodiments, a color image may include three RGB channels to define the color of each pixel (e.g., a red channel, a green channel, and a blue channel). Similarly, a filter for a color image may be represented by a 3D matrix with dimensions corresponding to the filter height (R), filter width (S), and channels (C) of the filter. In these embodiments, a convolution operation may be performed by moving the filter throughout the image and computing the dot product between the filter and the various portions of the image. For example, in some embodiments, the filter may be moved along the height and width of the image using a certain stride or interval, the dot product may be computed at each location, and the result may be stored in a corresponding location of a result matrix. Moreover, in some embodiments, when convolution operations need to be performed on multiple images using multiple filters, the images may be processed together to increase processing efficiency. Thus, in some embodiments, a collection of images may be represented using a four-dimensional (4D) matrix, with dimensions arranged into channels (C), height (H), width (W), and number of images (N). Similarly, a collection of filters may be represented using a 4D matrix, with dimensions arranged into channels (C), filter height (R), filter width (S), and number of filters (K). Accordingly, the convolution operations may then be performed using the 4D matrices that are used to represent the images and filters.

The matrix processing architecture of FIGS. 2A-2C may also be used to implement the matrix dimension shuffling functionality described throughout this disclosure. For example, in some embodiments, dimension shuffling may be implemented using matrix processing system 200. As discussed above, for example, matrix processing system 200 may be used to perform complex matrix operations, such as matrix multiplication and convolutions on matrix operands. The matrix operands may include matrices with two or more dimensions. For example, a matrix operand may be a matrix with two dimensions (e.g., a matrix with dimensions A and B, or A×B), or a matrix with three or more dimensions (e.g., a matrix with dimensions A, B, and C, or A×B×C). For example, in some embodiments, a three-dimensional (3D) matrix may be used to represent an image, and thus the dimensions A, B, and C may correspond to the channels (C), height (H), and width (W) of the image, as described above. Similarly, a four-dimensional (4D) matrix may be used to represent a collection of images, with dimensions arranged into channels (C), height (H), width (W), and number of images (N), as described above. The 3D matrix could also be used to represent a filter (e.g., for a convolution operation), and thus dimensions A, B, and C of the matrix may correspond to the channels (C), filter height (R), and filter width (S) of the filter. Similarly, a four-dimensional (4D) matrix could be used to represent a collection of filters used to perform convolution operations, with dimensions arranged into channels (C), filter height (R), filter width (S), and number of filters (K).

Moreover, matrix processing system 200 may include memory components designed to store the matrix operands, such as high bandwidth memory (HBM) modules 240 of FIG. 2B and/or memory resource blocks (MRBs) 238 of FIG. 2C. In some embodiments, the memory components of matrix processing system 200 may include two-dimensional (2D) memory components configured to store and retrieve data in two dimensions, such as using rows and columns. Accordingly, a 2D matrix (e.g., A×B) may be stored in 2D memory without rearranging the dimensions. However, for a matrix with three or more dimensions, the dimensions of the matrix may need to be rearranged in order to store the matrix in 2D memory. For example, a 3D matrix with dimensions A, B, and C (e.g., A×B×C) may be stored in 2D memory by treating two of the dimensions as a single dimension. For example, a 3D matrix with dimensions A×B×C may be stored in 2D memory with its dimensions arranged as AB×C, AC×B, BA×C, BC×A, or A×BC, and so forth. In some cases, however, a particular matrix operation (e.g., a convolution operation) may need the dimensions of a matrix converted from one arrangement in memory to another arrangement in memory (e.g., converting a matrix stored as AB×C to BA×C). As an example, a convolution operation may need the dimensions of its filter to be arranged differently for forward propagation operations versus backward propagation operations in an artificial neural network. Thus, in some embodiments, a dimension shuffle operation may be used to reorder the dimensions of a matrix in memory.

Dimension shuffle operations may be implemented by matrix processing system 200, for example, using strided memory access. For example, in some embodiments, a convolutional read operation may be implemented using matrix processing system 200. The convolutional read operation, for example, may use strided memory access to access data at locations in 2D memory that are separated by a particular interval or stride. For example, in some embodiments, the convolutional read operation may use strided memory access to access rows of 2D memory that are separated by a particular interval or stride, such as a particular number of rows. Similarly, in some embodiments, the convolutional read operation could use strided memory access to access columns of 2D memory that are separated by a particular interval or stride, such as a particular number of columns. The convolutional read operation may also begin the strided memory access at a particular offset within memory (e.g., a particular number of rows or columns from the beginning of 2D memory). Moreover, some embodiments may include multiple variations of the convolutional read operation, which may be used to store data obtained using strided memory access in different forms. For example, in some embodiments, a convolutional read operation may be used to implement both a non-transpose convolutional read and a transpose convolutional read. A non-transpose convolutional read, for example, may store data obtained using strided memory access in non-transpose form. A transpose convolutional read, for example, may store data obtained using strided memory access in transpose form. Accordingly, in some embodiments, non-transpose and transpose convolutional reads may be used to implement dimension shuffling operations. For example, a particular dimension shuffle operation may involve one or more non-transpose and/or transpose convolutional reads, and the result of each convolutional read may be stored in a result matrix based on the order in which the data is accessed using strided memory access. Moreover, in some cases, a particular dimension shuffle operation may involve multiple dimension shuffle operations to reorder the dimensions into one or more intermediate formats. For example, a dimension shuffle operation from AB×C to AC×B may involve a dimension shuffle from AB×C to BA×C, and another dimension shuffle from BA×C to AC×B. In this manner, any dimension shuffle operation may be performed using a combination of non-transpose and/or transpose convolutional reads to reorder the dimensions of a matrix from one format to another, while minimizing the number of conversions. In some embodiments, the result of the dimension shuffle operation may be stored in a result matrix, and the result matrix may be returned in response to a dimension shuffle operation or command.

The dimension shuffle operation may be implemented using any combination of hardware and/or software in matrix processing system 200. For example, in some embodiments, a convolutional read operation may be implemented using hardware (e.g., on MCC 232 and/or MPUs 234 of matrix processing cluster 230 of FIG. 2C), while the remaining dimension shuffle functionality (including the non-transpose and transpose variations of the convolutional read operation) may be implemented using software. In other embodiments, however, the dimension shuffle operation may be implemented entirely in hardware, entirely in software, or using any other combination of hardware and software.

Moreover, while the dimension shuffle operation described above is used to reorder the dimensions of a matrix stored in 2D memory, other embodiments may use memory components configured to store and retrieve data using any other number of dimensions (e.g., one dimension, three dimensions, four dimensions, and so forth).

Example Computer Processor Architectures

FIGS. 3 and 4 illustrate block diagrams for example embodiments of computer processors that may be used in accordance with embodiments disclosed herein. For example, the computer processors illustrated in FIGS. 3 and 4 may be used as host processors associated with matrix processing systems (e.g., host processor 260 in matrix processing system 200 of FIG. 2A), or as processors associated with other components and/or devices discussed throughout this disclosure (e.g., processors associated with components in system 100 of FIG. 1). Other processor and system designs and configurations known in the art for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices, are also suitable. In general, a huge variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable.

FIG. 3 illustrates a block diagram for an example embodiment of a processor 300. Processor 300 is an example of a type of hardware device that can be used in connection with the embodiments described throughout this disclosure. Processor 300 may be any type of processor, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a multi-core processor, a single core processor, or other device to execute code. Although only one processor 300 is illustrated in FIG. 3, a processing element may alternatively include more than one of processor 300 illustrated in FIG. 3. Processor 300 may be a single-threaded core or, for at least one embodiment, the processor 300 may be multi-threaded in that it may include more than one hardware thread context (or “logical processor”) per core.

FIG. 3 also illustrates a memory 302 coupled to processor 300 in accordance with an embodiment. Memory 302 may be any of a wide variety of memories (including various layers of memory hierarchy) as are known or otherwise available to those of skill in the art. Such memory elements can include, but are not limited to, random access memory (RAM), read only memory (ROM), logic blocks of a field programmable gate array (FPGA), erasable programmable read only memory (EPROM), and electrically erasable programmable ROM (EEPROM).

Processor 300 can execute any type of instructions associated with algorithms, processes, or operations detailed herein. Generally, processor 300 can transform an element or an article (e.g., data) from one state or thing to another state or thing.

Code 304, which may be one or more instructions to be executed by processor 300, may be stored in memory 302, or may be stored in software, hardware, firmware, or any suitable combination thereof, or in any other internal or external component, device, element, or object where appropriate and based on particular needs. In one example, processor 300 can follow a program sequence of instructions indicated by code 304. Each instruction enters a front-end logic 306 and is processed by one or more decoders 308. The decoder may generate, as its output, a micro operation such as a fixed width micro operation in a predefined format, or may generate other instructions, microinstructions, or control signals that reflect the original code instruction. Front-end logic 306 may also include register renaming logic and scheduling logic, which generally allocate resources and queue the operation corresponding to the instruction for execution.

Processor 300 can also include execution logic 314 having a set of execution units 316 a, 316 b, 316 n, etc. Some embodiments may include a number of execution units dedicated to specific functions or sets of functions. Other embodiments may include only one execution unit or one execution unit that can perform a particular function. Execution logic 314 performs the operations specified by code instructions.

After completion of execution of the operations specified by the code instructions, back-end logic 318 can retire the instructions of code 304. In one embodiment, processor 300 allows out of order execution but requires in order retirement of instructions. Retirement logic 320 may take a variety of known forms (e.g., re-order buffers or the like). In this manner, processor 300 is transformed during execution of code 304, at least in terms of the output generated by the decoder, hardware registers and tables utilized by register renaming logic 310, and any registers (not shown) modified by execution logic 314.

Although not shown in FIG. 3, a processing element may include other elements on a chip with processor 300. For example, a processing element may include memory control logic along with processor 300. The processing element may include I/O control logic and/or may include I/O control logic integrated with memory control logic. The processing element may also include one or more caches. In some embodiments, non-volatile memory (such as flash memory or fuses) may also be included on the chip with processor 300.

FIG. 4 illustrates a block diagram for an example embodiment of a multiprocessor 400. As shown in FIG. 4, multiprocessor system 400 is a point-to-point interconnect system, and includes a first processor 470 and a second processor 480 coupled via a point-to-point interconnect 450. In some embodiments, each of processors 470 and 480 may be some version of processor 300 of FIG. 3.

Processors 470 and 480 are shown including integrated memory controller (IMC) units 472 and 482, respectively. Processor 470 also includes as part of its bus controller units point-to-point (P-P) interfaces 476 and 478; similarly, second processor 480 includes P-P interfaces 486 and 488. Processors 470, 480 may exchange information via a point-to-point (P-P) interface 450 using P-P interface circuits 478, 488. As shown in FIG. 4, IMCs 472 and 482 couple the processors to respective memories, namely a memory 432 and a memory 434, which may be portions of main memory locally attached to the respective processors.

Processors 470, 480 may each exchange information with a chipset 490 via individual P-P interfaces 452, 454 using point to point interface circuits 476, 494, 486, 498. Chipset 490 may optionally exchange information with the coprocessor 438 via a high-performance interface 439. In one embodiment, the coprocessor 438 is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, matrix processor, or the like.

A shared cache (not shown) may be included in either processor or outside of both processors, yet connected with the processors via P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.

Chipset 490 may be coupled to a first bus 416 via an interface 496. In one embodiment, first bus 416 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of this disclosure is not so limited.

As shown in FIG. 4, various I/O devices 414 may be coupled to first bus 416, along with a bus bridge 418 which couples first bus 416 to a second bus 420. In one embodiment, one or more additional processor(s) 415, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), matrix processors, field programmable gate arrays, or any other processor, are coupled to first bus 416. In one embodiment, second bus 420 may be a low pin count (LPC) bus. Various devices may be coupled to a second bus 420 including, for example, a keyboard and/or mouse 422, communication devices 427 and a storage unit 428 such as a disk drive or other mass storage device which may include instructions/code and data 430, in one embodiment. Further, an audio I/O 424 may be coupled to the second bus 420. Note that other architectures are possible. For example, instead of the point-to-point architecture of FIG. 4, a system may implement a multi-drop bus or other such architecture.

All or part of any component of FIG. 4 may be implemented as a separate or stand-alone component or chip, or may be integrated with other components or chips, such as a system-on-a-chip (SoC) that integrates various computer components into a single chip.

Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Certain embodiments may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

Program code, such as code 430 illustrated in FIG. 4, may be applied to input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices, in known fashion. For purposes of this application, a processing system includes any system that has a processor, such as, for example; a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

The program code may be implemented in a high level procedural or object oriented programming language to communicate with a processing system. The program code may also be implemented in assembly or machine language, if desired. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled or interpreted language.

One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium which represents various logic within the processor, which when read by a machine causes the machine to fabricate logic to perform the techniques described herein. Such representations, known as “IP cores” may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor.

Such machine-readable storage media may include, without limitation, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, including storage media such as hard disks, any other type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritable's (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), phase change memory (PCM), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.

Accordingly, embodiments of this disclosure also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such embodiments may also be referred to as program products.

Matrix Dimension Shuffling

FIGS. 5A-D illustrate examples of matrix dimension shuffling. In some embodiments, these example operations may be performed using a matrix processing architecture, such as the matrix processing architecture of FIGS. 2A-2C.

In the illustrated examples, dimension shuffling is performed for a three-dimensional (3D) matrix stored in two-dimensional (2D) memory. The example 3D matrix includes dimensions A, B, and C (or A×B×C). In the illustrated examples, the 3D matrix is stored in 2D memory with its dimensions arranged as AB×C, and dimension shuffling is used to reorder the dimensions into other 2D permutations, such as from AB×C to BA×C, and from AB×C to BC×A.

In some embodiments, the 3D matrix could be used to represent an image, and thus dimensions A, B, and C of the matrix may correspond to the channels (C), height (H), and width (W) of the image (or C×H×W). The 3D matrix could also be used to represent a filter (e.g., for a convolution operation), and thus dimensions A, B, and C of the matrix may correspond to the channels (C), filter height (R), and filter width (S) of the filter (or C×R×S). Moreover, while the examples illustrated by FIGS. 5A-D use a 3D matrix, a matrix with any number of dimensions may be used. For example, in some embodiments, a four-dimensional (4D) matrix could be used to represent a collection of images, with dimensions arranged into channels (C), height (H), width (W), and number of images (N) (or C×H×W×N). Alternatively, a four-dimensional (4D) matrix could be used to represent a collection of filters used to perform convolution operations, with dimensions arranged into channels (C), filter height (R), filter width (S), and number of filters (K) (or C×R×S×K). Accordingly, dimension shuffling could be used to reorder the dimensions of a matrix used to represent an image, a filter, or a collection of images or filters. For example, a matrix used to represent a collection of filters could be stored in 2D memory with its dimensions arranged as CRS×K, and dimension shuffling could be used to reorder the dimensions to any other 2D permutation, such as from CRS×K to KRS×C.

FIG. 5A illustrates an example of a three-dimensional (3D) matrix 500A. In the illustrated embodiment, matrix 500A includes dimensions A, B, and C, or A×B×C. Dimension A includes elements a₀ and a₁; dimension B includes elements b₀, b₁, and b₂; and dimension C includes elements c₀, c₁, and c₂.

FIG. 5B illustrates an example of how 3D matrix 500A of FIG. 5A may be stored in two-dimensional (2D) memory as 2D matrix 500B. For example, in some embodiments, matrix operands may be stored using two-dimensional (2D) memory components (e.g., memory configured to store and retrieve data in two dimensions, such as using rows and columns). Accordingly, a matrix with three or more dimensions (e.g., matrix 500A of FIG. 5A) may need its dimensions rearranged in order for the matrix to be stored in 2D memory. For example, 3D matrix 500A (which includes dimensions A, B, and C, or A×B×C) may be stored in 2D memory as 2D matrix 500B by treating two of its dimensions as a single dimension. For example, 3D matrix 500A may be stored in 2D memory as 2D matrix 500B by arranging its dimensions as AB×C, AC×B, BA×C, BC×A, or A×BC, and so forth. In the illustrated embodiment, for example, 3D matrix 500A is stored as 2D matrix 500B by treating dimensions A and B as one dimension in 2D memory, and treating dimension C as another dimension in 2D memory, or AB×C.

In some cases, however, a particular matrix operation (e.g., a convolution operation) may need the dimensions of matrix 500A converted from one arrangement in memory to another arrangement in memory (e.g., converting a matrix from AB×C to BA×C). As an example, a convolution operation may need the dimensions of its filter to be arranged differently for forward propagation operations versus backward propagation operations in an artificial neural network. Accordingly, a dimension shuffle operation may be used to reorder the dimensions of a matrix in memory.

In some embodiments, a dimension shuffle operation may be implemented using convolutional read operations and/or strided memory access. For example, in some embodiments, a matrix processing system (e.g., matrix processing system 200 of FIG. 2A) may implement a convolutional read operation, which may use strided memory access to access data at locations in 2D memory that are separated by a particular interval or stride. A convolutional read operation may also begin the strided memory access at a particular offset within memory. Moreover, some embodiments may include multiple variations of a convolutional read operation, including non-transpose and transpose convolutional reads. A non-transpose convolutional read, for example, may store data obtained using strided memory access in non-transpose form (e.g., as illustrated in FIG. 5C). A transpose convolutional read, for example, may store data obtained using strided memory access in transpose form (e.g., as illustrated in FIG. 5D).

A particular dimension shuffle operation may involve one or more non-transpose and/or transpose convolutional reads, and the result of each convolutional read may be stored in a result matrix based on the order in which the data is accessed using strided memory access. Moreover, in some cases, a particular dimension shuffle operation may involve multiple dimension shuffle operations to reorder the dimensions into one or more intermediate formats. For example, a dimension shuffle operation from AB×C to AC×B may involve a dimension shuffle from AB×C to BA×C, and another dimension shuffle from BA×C to AC×B. In this manner, any dimension shuffle operation may be performed using a combination of non-transpose and/or transpose convolutional reads to reorder the dimensions of a matrix from one format to another.

FIG. 5C illustrates an example of matrix dimension shuffling using non-transpose convolutional read operations. In the illustrated example, matrix 500C-1 corresponds to a 3D matrix (e.g., 3D matrix 500A of FIG. 5A) that is stored in 2D memory with its dimensions arranged as AB×C. Similarly, matrix 500C-2 corresponds to the same matrix but with its dimensions arranged as BA×C. In some embodiments, matrix 500C-1 may be converted into matrix 500C-2, or from AB×C to BA×C, using non-transpose convolutional read operations.

In the illustrated example, a non-transpose convolutional read operation is used to access certain data of matrix 500C-1 and store the data in matrix 500C-2. In the illustrated example, the non-transpose convolution read operation uses strided memory access with an offset of zero and a stride of three rows. Accordingly, because the offset is zero, the convolutional read begins by accessing the first row of matrix 500C-1 and storing it in non-transpose form as the first row of matrix 500C-2 (as depicted by operation 505-1). Next, because the stride is three rows, the convolutional read then accesses the fourth row of matrix 500C-1 and stores it in non-transpose form as the second row of matrix 500C-2 (as depicted by operation 505-2). The next strided memory access of the convolutional read would occur at the seventh row, but because matrix 500C-1 only contains six rows, the convolutional read is complete.

Although not illustrated, the dimension shuffle operation can be completed using two additional non-transpose convolutional read operations, using the same stride (e.g., three) but with offsets of one and two for the respective convolutional read operations. For example, a non-transpose convolutional read operation with an offset of one and a stride of three would access the second and fifth rows of matrix 500C-1, and store them in non-transpose form as the third and fourth rows of matrix 500C-2, respectively. Similarly, a non-transpose convolutional read operation with an offset of two and a stride of three would access the third and sixth rows of matrix 500C-1, and store them in non-transpose form as the fifth and sixth rows of matrix 500C-2, respectively. At this point, the dimension shuffle operation would be complete.

FIG. 5D illustrates an example of matrix dimension shuffling using transpose convolutional read operations. In the illustrated example, matrix 500D-1 corresponds to a 3D matrix (e.g., 3D matrix 500A of FIG. 5A) that is stored in 2D memory with its dimensions arranged as AB×C. Similarly, matrix 500D-2 corresponds to the same matrix but with its dimensions arranged as BC×A. In some embodiments, matrix 500D-1 may be converted into matrix 500D-2, or from AB×C to BC×A, using convolutional read operations.

In the illustrated example, a transpose convolutional read operation is used to access certain data of matrix 500D-1 and store the data in matrix 500D-2. In the illustrated example, the transpose convolution read operation uses strided memory access with an offset of zero and a stride of three rows. Accordingly, because the offset is zero, the convolutional read begins by accessing the first row of matrix 500D-1 and storing it in transpose form at the beginning of the first column of matrix 500D-2 (as depicted by operation 506-1). For example, the first row of matrix 500D-1 contains three elements, and thus the transposed form is a column with three elements, which is then stored as the first three elements of the first column of matrix 500D-2. Next, because the stride is three rows, the convolutional read then accesses the fourth row of matrix 500D-1 and stores it in transpose form at the beginning of the second column of matrix 500D-2 (as depicted by operation 506-2). For example, the fourth row of matrix 500D-1 contains three elements, and thus the transposed form is a column with three elements, which is then stored as the first three elements of the second column of matrix 500D-2. The next strided memory access of the convolutional read would occur at the seventh row, but because matrix 500D-1 only contains six rows, the convolutional read is complete.

Although not illustrated, the dimension shuffle operation can be completed using two additional transpose convolutional read operations, using the same stride (e.g., three) but with offsets of one and two for the respective convolutional read operations. For example, a transpose convolutional read operation with an offset of one and a stride of three would access the second and fifth rows of matrix 500D-1, and store them in transpose form in the next available elements (e.g., elements four through six) of the first and second columns of matrix 500D-2, respectively. Similarly, a transpose convolutional read operation with an offset of two and a stride of three would access the third and sixth rows of matrix 500D-1, and store them in transpose form in the next available elements (e.g., elements seven through nine) of the first and second columns of matrix 500D-2, respectively. At this point, the dimension shuffle operation would be complete.

FIG. 6 illustrates a flowchart 600 for an example embodiment of matrix dimension shuffling. Flowchart 600 may be implemented, in some embodiments, by components described throughout this disclosure (e.g., the matrix processing architecture of FIGS. 2A-C).

The flowchart may begin at block 602 by receiving a command to perform a matrix dimension shuffle operation. The matrix dimension shuffle operation, for example, may be an operation to reorder a plurality of dimensions of an input matrix. In some embodiments, for example, the input matrix may be stored in two-dimensional (2D) memory. Moreover, in some cases, the input matrix may include two-dimensions. In other cases, however, the input matrix may contain a number of dimensions other than two dimensions, such as three dimensions, four dimensions, or any other number of dimensions. Moreover, in some embodiments, the matrix dimension shuffle operation may be associated with another complex matrix operation, such as a convolution operation associated with backward propagation in an artificial neural network.

The flowchart may then proceed to block 604 to perform a strided memory access operation. For example, in some embodiments, the strided memory access operation may be a convolutional read operation. The convolutional read operation, for example, may use strided memory access to access data at locations in memory that are separated by a particular interval or stride. For example, in some embodiments, the convolutional read operation may use strided memory access to access rows of memory that are separated by a particular interval or stride, such as a particular number of rows. Similarly, in some embodiments, the convolutional read operation could use strided memory access to access columns of memory that are separated by a particular interval or stride, such as a particular number of columns. The convolutional read operation may also begin the strided memory access at a particular offset within memory (e.g., a particular number of rows or columns from the beginning of memory).

The flowchart may then proceed to block 606 to determine whether the data accessed using the strided memory access operation should be stored in non-transpose form or transpose form. For example, some embodiments may include multiple variations of a convolutional read operation, including non-transpose and transpose convolutional reads. A non-transpose convolutional read, for example, may store data obtained using strided memory access in non-transpose form. A transpose convolutional read, for example, may store data obtained using strided memory access in transpose form.

If it is determined at block 606 that the data should be stored in non-transpose form, the flowchart may then proceed to block 608 to store the data in a result matrix in non-transpose form.

If it is determined at block 606 that the data should be stored in transpose form, the flowchart may then proceed to block 610 to store the data in a result matrix in transpose form.

The flowchart may then proceed to block 612 to determine whether the dimension shuffle operation has been completed. If it is determined at block 612 that the dimension shuffle operation is incomplete, the flowchart may then proceed to block 604 to continue performing strided memory access operations. For example, a particular dimension shuffle operation may involve one or more non-transpose and/or transpose convolutional reads, and the result of each convolutional read may be stored in a result matrix based on the order in which the data is accessed using strided memory access. Moreover, in some cases, a particular dimension shuffle operation may involve multiple dimension shuffle operations to reorder the dimensions into one or more intermediate formats. In this manner, any dimension shuffle operation may be performed using a combination of non-transpose and/or transpose convolutional reads to reorder the dimensions of a matrix from one format to another.

If it is determined at block 612 that the dimension shuffle operation has been completed, the result matrix may be returned in response to the command to perform the dimension shuffle operation.

At this point, the flowchart may be complete. In some embodiments, however, the flowchart may restart and/or certain blocks may be repeated. For example, in some embodiments, the flowchart may restart at block 602 to continue receiving and processing commands to perform matrix dimension shuffle operations.

The flowcharts and block diagrams in the FIGURES illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various aspects of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order or alternative orders, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The foregoing disclosure outlines features of several embodiments so that those skilled in the art may better understand various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

All or part of any hardware element disclosed herein may readily be provided in a system-on-a-chip (SoC), including a central processing unit (CPU) package. An SoC represents an integrated circuit (IC) that integrates components of a computer or other electronic system into a single chip. The SoC may contain digital, analog, mixed-signal, and radio frequency functions, all of which may be provided on a single chip substrate. Other embodiments may include a multi-chip-module (MCM), with a plurality of chips located within a single electronic package and configured to interact closely with each other through the electronic package. In various other embodiments, the computing functionalities disclosed herein may be implemented in one or more silicon cores in Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), and other semiconductor chips.

As used throughout this specification, the term “processor” or “microprocessor” should be understood to include not only a traditional microprocessor (such as Intel's® industry-leading x86 and x64 architectures), but also matrix processors, graphics processors, and any ASIC, FPGA, microcontroller, digital signal processor (DSP), programmable logic device, programmable logic array (PLA), microcode, instruction set, emulated or virtual machine processor, or any similar “Turing-complete” device, combination of devices, or logic elements (hardware or software) that permit the execution of instructions.

Note also that in certain embodiments, some of the components may be omitted or consolidated. In a general sense, the arrangements depicted in the figures should be understood as logical divisions, whereas a physical architecture may include various permutations, combinations, and/or hybrids of these elements. It is imperative to note that countless possible design configurations can be used to achieve the operational objectives outlined herein. Accordingly, the associated infrastructure has a myriad of substitute arrangements, design choices, device possibilities, hardware configurations, software implementations, and equipment options.

In a general sense, any suitably-configured processor can execute instructions associated with data or microcode to achieve the operations detailed herein. Any processor disclosed herein could transform an element or an article (for example, data) from one state or thing to another state or thing. In another example, some activities outlined herein may be implemented with fixed logic or programmable logic (for example, software and/or computer instructions executed by a processor) and the elements identified herein could be some type of a programmable processor, programmable digital logic (for example, a field programmable gate array (FPGA), an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM)), an ASIC that includes digital logic, software, code, electronic instructions, flash memory, optical disks, CD-ROMs, DVD ROMs, magnetic or optical cards, other types of machine-readable mediums suitable for storing electronic instructions, or any suitable combination thereof.

In operation, a storage may store information in any suitable type of tangible, non-transitory storage medium (for example, random access memory (RAM), read only memory (ROM), field programmable gate array (FPGA), erasable programmable read only memory (EPROM), electrically erasable programmable ROM (EEPROM), or microcode), software, hardware (for example, processor instructions or microcode), or in any other suitable component, device, element, or object where appropriate and based on particular needs. Furthermore, the information being tracked, sent, received, or stored in a processor could be provided in any database, register, table, cache, queue, control list, or storage structure, based on particular needs and implementations, all of which could be referenced in any suitable timeframe. Any of the memory or storage elements disclosed herein should be construed as being encompassed within the broad terms ‘memory’ and ‘storage,’ as appropriate. A non-transitory storage medium herein is expressly intended to include any non-transitory special-purpose or programmable hardware configured to provide the disclosed operations, or to cause a processor to perform the disclosed operations. A non-transitory storage medium also expressly includes a processor having stored thereon hardware-coded instructions, and optionally microcode instructions or sequences encoded in hardware, firmware, or software.

Computer program logic implementing all or part of the functionality described herein is embodied in various forms, including, but in no way limited to, hardware description language, a source code form, a computer executable form, machine instructions or microcode, programmable hardware, and various intermediate forms (for example, forms generated by an HDL processor, assembler, compiler, linker, or locator). In an example, source code includes a series of computer program instructions implemented in various programming languages, such as an object code, an assembly language, or a high-level language such as OpenCL, FORTRAN, C, C++, JAVA, or HTML for use with various operating systems or operating environments, or in hardware description languages such as Spice, Verilog, and VHDL. The source code may define and use various data structures and communication messages. The source code may be in a computer executable form (e.g., via an interpreter), or the source code may be converted (e.g., via a translator, assembler, or compiler) into a computer executable form, or converted to an intermediate form such as byte code. Where appropriate, any of the foregoing may be used to build or describe appropriate discrete or integrated circuits, whether sequential, combinatorial, state machines, or otherwise.

In one example, any number of electrical circuits of the FIGURES may be implemented on a board of an associated electronic device. The board can be a general circuit board that can hold various components of the internal electronic system of the electronic device and, further, provide connectors for other peripherals. More specifically, the board can provide the electrical connections by which the other components of the system can communicate electrically. Any suitable processor and memory can be suitably coupled to the board based on particular configuration needs, processing demands, and computing designs. Other components such as external storage, additional sensors, controllers for audio/video display, and peripheral devices may be attached to the board as plug-in cards, via cables, or integrated into the board itself. In another example, the electrical circuits of the FIGURES may be implemented as stand-alone modules (e.g., a device with associated components and circuitry configured to perform a specific application or function) or implemented as plug-in modules into application specific hardware of electronic devices.

Note that with the numerous examples provided herein, interaction may be described in terms of two, three, four, or more electrical components. However, this has been done for purposes of clarity and example only. It should be appreciated that the system can be consolidated or reconfigured in any suitable manner. Along similar design alternatives, any of the illustrated components, modules, and elements of the FIGURES may be combined in various possible configurations, all of which are within the broad scope of this specification. In certain cases, it may be easier to describe one or more of the functionalities of a given set of flows by only referencing a limited number of electrical elements. It should be appreciated that the electrical circuits of the FIGURES and its teachings are readily scalable and can accommodate a large number of components, as well as more complicated/sophisticated arrangements and configurations. Accordingly, the examples provided should not limit the scope or inhibit the broad teachings of the electrical circuits as potentially applied to a myriad of other architectures.

Numerous other changes, substitutions, variations, alterations, and modifications may be ascertained to one skilled in the art and it is intended that the present disclosure encompass all such changes, substitutions, variations, alterations, and modifications as falling within the scope of the appended claims.

Example Implementations

The following examples pertain to embodiments described throughout this disclosure.

One or more embodiments may include an apparatus, comprising: a memory element comprising two-dimensional memory; and a processor to perform a matrix operation to reorder a plurality of dimensions of an input matrix stored in two-dimensional memory, wherein the processor is configured to: access data associated with the input matrix using one or more strided memory operations, wherein the one or more strided memory operations are configured to access the two-dimensional memory at a plurality of locations that are separated by a particular interval; and store the data accessed using the one or more strided memory operations in a result matrix, wherein the data accessed using each strided memory operation is stored in the result matrix in non-transpose form or transpose form.

In one example embodiment of an apparatus, the matrix operation comprises a dimension shuffle operation to reorder the plurality of dimensions of the input matrix.

In one example embodiment of an apparatus, the one or more strided memory operations are configured to access the two-dimensional memory at a plurality of rows that are separated by the particular interval, wherein the particular interval comprises a particular number of rows.

In one example embodiment of an apparatus, the one or more strided memory operations are configured to access the two-dimensional memory at a plurality of columns that are separated by the particular interval, wherein the particular interval comprises a particular number of columns.

In one example embodiment of an apparatus: the one or more strided memory operations are each configured to begin accessing the two-dimensional memory at a particular offset; and the processor is further configured to store the data in the result matrix based on an order in which the data is accessed using the one or more strided memory operations.

In one example embodiment of an apparatus, the one or more strided memory operations comprise one or more convolutional read operations, the one or more convolutional read operations comprising at least one of: a non-transpose convolutional read, wherein data accessed using the non-transpose convolutional read is stored in the result matrix in non-transpose form; or a transpose convolutional read, wherein data accessed using the transpose convolutional read is stored in the result matrix in transpose form.

In one example embodiment of an apparatus, the one or more convolutional read operations comprise at least one non-transpose convolutional read and at least one transpose convolutional read.

In one example embodiment of an apparatus: the non-transpose form comprises a same form in which the data is accessed in the two-dimensional memory; and the transpose form comprises a form in which the data accessed in the two-dimensional memory is transposed.

In one example embodiment of an apparatus, the matrix operation is associated with a convolution operation in a neural network.

In one example embodiment of an apparatus, the matrix operation is associated with a backward propagation operation in a neural network.

One or more embodiments may include a method, comprising: performing a matrix operation to reorder a plurality of dimensions of an input matrix stored in two-dimensional memory, wherein performing the matrix operation comprises: accessing data associated with the input matrix using one or more strided memory operations, wherein the one or more strided memory operations are configured to access the two-dimensional memory at a plurality of locations that are separated by a particular interval; and storing the data accessed using the one or more strided memory operations in a result matrix, wherein the data accessed using each strided memory operation is stored in the result matrix in non-transpose form or transpose form.

In one example embodiment of a method, the matrix operation comprises a dimension shuffle operation to reorder the plurality of dimensions of the input matrix.

In one example embodiment of a method, the one or more strided memory operations are configured to access the two-dimensional memory at a plurality of rows that are separated by the particular interval, wherein the particular interval comprises a particular number of rows.

In one example embodiment of a method, the one or more strided memory operations are configured to access the two-dimensional memory at a plurality of columns that are separated by the particular interval, wherein the particular interval comprises a particular number of columns.

In one example embodiment of a method, the one or more strided memory operations each begin accessing the two-dimensional memory at a particular offset.

In one example embodiment of a method, the data is ordered in the result matrix based on an order in which the data is accessed using the one or more strided memory operations.

In one example embodiment of a method, the one or more strided memory operations comprise one or more convolutional read operations, the one or more convolutional read operations comprising at least one of: a non-transpose convolutional read, wherein data accessed using the non-transpose convolutional read is stored in the result matrix in non-transpose form; or a transpose convolutional read, wherein data accessed using the transpose convolutional read is stored in the result matrix in transpose form.

In one example embodiment of a method, the one or more convolutional read operations comprise at least one non-transpose convolutional read and at least one transpose convolutional read.

In one example embodiment of a method: the non-transpose form comprises a same form in which the data is accessed in the two-dimensional memory; and the transpose form comprises a form in which the data accessed in the two-dimensional memory is transposed.

In one example embodiment of a method, the matrix operation is associated with a convolution operation in a neural network.

In one example embodiment of a method, the matrix operation is associated with a backward propagation operation in a neural network.

In one example embodiment of a method, the method further comprises returning the result matrix in response to the command to perform the matrix operation.

One or more embodiments may include a system, comprising: a memory element comprising two-dimensional memory; a plurality of processing elements, comprising: a host processor; one or more matrix processing chips; a plurality of matrix processors associated with the one or more matrix processing chips; wherein a matrix processor of the plurality of matrix processors is to perform a matrix operation to reorder a plurality of dimensions of an input matrix stored in two-dimensional memory, wherein the matrix processor is configured to: access data associated with the input matrix using one or more strided memory operations, wherein the one or more strided memory operations are configured to access the two-dimensional memory at a plurality of locations that are separated by a particular interval; and store the data accessed using the one or more strided memory operations in a result matrix, wherein the data accessed using each strided memory operation is stored in the result matrix in non-transpose form or transpose form.

In one example embodiment of a system, the one or more strided memory operations comprise a plurality of convolutional read operations, the plurality of convolutional read operations comprising: a non-transpose convolutional read, wherein data accessed using the non-transpose convolutional read is to be stored in the result matrix in non-transpose form; and a transpose convolutional read, wherein data accessed using the transpose convolutional read is to be stored in the result matrix in transpose form.

One or more embodiments may include at least one machine accessible storage medium having instructions stored thereon, the instructions, when executed on a machine, cause the machine to: perform a matrix operation to reorder a plurality of dimensions of an input matrix stored in two-dimensional memory, wherein the instructions that cause the machine to perform the matrix operation further cause the machine to: access data associated with the input matrix using one or more strided memory operations, wherein the one or more strided memory operations are configured to access the two-dimensional memory at a plurality of locations that are separated by a particular interval; and store the data accessed using the one or more strided memory operations in a result matrix, wherein the data accessed using each strided memory operation is stored in the result matrix in non-transpose form or transpose form.

In one example embodiment of a storage medium, the matrix operation comprises a dimension shuffle operation to reorder the plurality of dimensions of the input matrix.

In one example embodiment of a storage medium, the one or more strided memory operations are configured to access the two-dimensional memory at a plurality of rows that are separated by the particular interval, wherein the particular interval comprises a particular number of rows.

In one example embodiment of a storage medium, the one or more strided memory operations are configured to access the two-dimensional memory at a plurality of columns that are separated by the particular interval, wherein the particular interval comprises a particular number of columns.

In one example embodiment of a storage medium: the one or more strided memory operations are each configured to begin accessing the two-dimensional memory at a particular offset; and wherein the instructions further cause the machine to store the data in the result matrix based on an order in which the data is accessed using the one or more strided memory operations.

In one example embodiment of a storage medium, the one or more strided memory operations comprise a plurality of convolutional read operations, the plurality of convolutional read operations comprising: a non-transpose convolutional read, wherein data accessed using the non-transpose convolutional read is stored in the result matrix in non-transpose form; and a transpose convolutional read, wherein data accessed using the transpose convolutional read is stored in the result matrix in transpose form.

In one example embodiment of a storage medium: the non-transpose form comprises a same form in which the data is accessed in the two-dimensional memory; and the transpose form comprises a form in which the data accessed in the two-dimensional memory is transposed.

One or more embodiments may include an apparatus comprising means to perform a method in any of the preceding examples.

One or more embodiments may include at least one machine accessible storage medium having instructions stored thereon, the instructions, when executed on a machine, cause the machine to: perform a method or realize an apparatus from any of the preceding examples. 

What is claimed is:
 1. An apparatus, comprising: a memory element comprising two-dimensional memory; and a processor to perform a matrix operation to reorder a plurality of dimensions of an input matrix stored in two-dimensional memory, wherein the processor is configured to: access data associated with the input matrix using a plurality of strided memory operations, wherein the plurality of strided memory operations are configured to access the two-dimensional memory at a plurality of locations that are separated by a particular interval, and wherein the plurality of strided memory operations comprise: at least one non-transpose convolutional read, wherein data accessed using the at least one non-transpose convolutional read is to be stored in non-transpose form; and at least one transpose convolutional read, wherein data accessed using the at least one transpose convolutional read is to be stored in transpose form; and store the data accessed using the plurality of strided memory operations in a result matrix, wherein the data accessed using each strided memory operation is stored in the result matrix in non-transpose form or transpose form.
 2. The apparatus of claim 1, wherein the matrix operation comprises a dimension shuffle operation to reorder the plurality of dimensions of the input matrix.
 3. The apparatus of claim 1, wherein the plurality of strided memory operations are configured to access the two-dimensional memory at a plurality of rows that are separated by the particular interval, wherein the particular interval comprises a particular number of rows.
 4. The apparatus of claim 1, wherein the plurality of strided memory operations are configured to access the two-dimensional memory at a plurality of columns that are separated by the particular interval, wherein the particular interval comprises a particular number of columns.
 5. The apparatus of claim 1: wherein the plurality of strided memory operations are each configured to begin accessing the two-dimensional memory at a particular offset; and wherein the processor is further configured to store the data in the result matrix based on an order in which the data is accessed using the plurality of strided memory operations.
 6. The apparatus of claim 1: wherein the non-transpose form comprises a same form in which the data is accessed in the two-dimensional memory; and wherein the transpose form comprises a form in which the data accessed in the two-dimensional memory is transposed.
 7. The apparatus of claim 1, wherein the matrix operation is associated with a convolution operation in a neural network.
 8. The apparatus of claim 1, wherein the matrix operation is associated with a backward propagation operation in a neural network.
 9. A method performed by a matrix processor, comprising: performing a matrix operation to reorder a plurality of dimensions of an input matrix stored in two-dimensional memory circuitry, wherein performing the matrix operation comprises: accessing data associated with the input matrix using a plurality of strided memory operations, wherein the plurality of strided memory operations are configured to access the two-dimensional memory circuitry at a plurality of locations that are separated by a particular interval, and wherein the plurality of strided memory operations comprise: at least one non-transpose convolutional read, wherein data accessed using the at least one non-transpose convolutional read is to be stored in non-transpose form; and at least one transpose convolutional read, wherein data accessed using the at least one transpose convolutional read is to be stored in transpose form; and storing the data accessed using the plurality of strided memory operations in a result matrix, wherein the data accessed using each strided memory operation is stored in the result matrix in non-transpose form or transpose form.
 10. The method of claim 9, wherein the matrix operation comprises a dimension shuffle operation to reorder the plurality of dimensions of the input matrix.
 11. The method of claim 9, wherein the plurality of strided memory operations are configured to access the two-dimensional memory circuitry at a plurality of rows that are separated by the particular interval, wherein the particular interval comprises a particular number of rows.
 12. The method of claim 9, wherein the plurality of strided memory operations are configured to access the two-dimensional memory circuitry at a plurality of columns that are separated by the particular interval, wherein the particular interval comprises a particular number of columns.
 13. The method of claim 9: wherein the plurality of strided memory operations each begin accessing the two-dimensional memory circuitry at a particular offset; and wherein the data is stored in the result matrix based on an order in which the data is accessed using the plurality of strided memory operations.
 14. A system, comprising: a memory element comprising two-dimensional memory; a plurality of processing elements, comprising: a host processor; one or more matrix processing chips; a plurality of matrix processors associated with the one or more matrix processing chips; wherein a matrix processor of the plurality of matrix processors is to perform a matrix operation to reorder a plurality of dimensions of an input matrix stored in two-dimensional memory, wherein the matrix processor is configured to: access data associated with the input matrix using a plurality of strided memory operations, wherein the plurality of strided memory operations are configured to access the two-dimensional memory at a plurality of locations that are separated by a particular interval, and wherein the plurality of strided memory operations comprise: at least one non-transpose convolutional read, wherein data accessed using the at least one non-transpose convolutional read is to be stored in non-transpose form; and at least one transpose convolutional read, wherein data accessed using the at least one transpose convolutional read is to be stored in transpose form; and store the data accessed using the plurality of strided memory operations in a result matrix, wherein the data accessed using each strided memory operation is stored in the result matrix in non-transpose form or transpose form.
 15. At least one non-transitory machine accessible storage medium having instructions stored thereon, the instructions, when executed on a machine, cause the machine to: perform a matrix operation to reorder a plurality of dimensions of an input matrix stored in two-dimensional memory, wherein the instructions that cause the machine to perform the matrix operation further cause the machine to: access data associated with the input matrix using a plurality of strided memory operations, wherein the plurality of strided memory operations are configured to access the two-dimensional memory at a plurality of locations that are separated by a particular interval, and wherein the plurality of strided memory operations comprise: at least one non-transpose convolutional read, wherein data accessed using the at least one non-transpose convolutional read is to be stored in non-transpose form; and at least one transpose convolutional read, wherein data accessed using the at least one transpose convolutional read is to be stored in transpose form; and store the data accessed using the plurality of strided memory operations in a result matrix, wherein the data accessed using each strided memory operation is stored in the result matrix in non-transpose form or transpose form.
 16. The storage medium of claim 15, wherein the matrix operation comprises a dimension shuffle operation to reorder the plurality of dimensions of the input matrix.
 17. The storage medium of claim 15, wherein the plurality of strided memory operations are configured to access the two-dimensional memory at a plurality of rows that are separated by the particular interval, wherein the particular interval comprises a particular number of rows.
 18. The storage medium of claim 15, wherein the plurality of strided memory operations are configured to access the two-dimensional memory at a plurality of columns that are separated by the particular interval, wherein the particular interval comprises a particular number of columns.
 19. The storage medium of claim 15: wherein the plurality of strided memory operations are each configured to begin accessing the two-dimensional memory at a particular offset; and wherein the instructions further cause the machine to store the data in the result matrix based on an order in which the data is accessed using the plurality of strided memory operations.
 20. The storage medium of claim 15: wherein the non-transpose form comprises a same form in which the data is accessed in the two-dimensional memory; and wherein the transpose form comprises a form in which the data accessed in the two-dimensional memory is transposed. 